The present invention relates to a pipeline-controlled type information processing system (PIP system).
Generally, in a PIP system, the success/failure of branching is determined at the time of execution of a conditional branch instruction in response to the end of execution of an instruction immediately before the conditional branch instruction and by referring to a condition code after the execution of the immediately preceding instruction. For high-speed processing of a conditional branch instruction, therefore, it is a primary requisite that the condition code to be referred to be determined within a short period of time.
A technique for fast determination of a condition code is disclosed in the U.S. Pat. No. 3,881,173. In accordance with the disclosed technique, fast condition code determination is achieved by use of specially designed hardware which quickly calculates a condition code only prior to execution of an operation, which should occur during the execution of an operation instruction for updating the condition code. Such an implementation, however, is not applicable to a PIP system in which an operation instruction cannot quickly determine only a condition code before execution of the operation or, if this can be done, requires a considerable amount of hardware for the determination.
A system applicable even to such a system is described in the Japanese Patent Publication No. 2741/1981. This system is based on the fact that the instructions include one which does not update a condition code. That is, the system is furnished with hardware responsive to whether or not a specific one of the instructions, preceding a conditional branch instruction which updates a condition code last, has completed an operation phase. A control in this system occurs such that a response is provided, not to the end of execution of an instruction just before a conditional branch instruction, but, to the end of execution of an instruction which determines a condition code to be referred to in response to a conditional branch instruction, thereby speeding up the determination of success/failure of a conditional branch instruction.
Another PIP system which achieves an improvement over the above-described technique, is disclosed in the Japanese Patent disclosure No. 158745/1983. What underlies this system is the fact that address calculation associated with memory operands or access to a cache memory is needless when an instruction for causing an operation between general purpose registers is to be executed. The system includes a circuit for generating a condition code for an instruction adapted to cause an operation between general purpose registers in a memory operand address calculation phase, and a circuit for generating a condition code for a shift instruction adapted to shift data stored in a general purpose register by a quantity indicated by a result of address calculation in a cache memory access phase. Determination of a condition code in the operation instruction or the shift instruction occurs before that of a condition code associated with an instruction other than the two which cause a memory operand operation. The system further includes, in the respective phases in the pipeline processing procedure, means for indicating whether or not an instruction in the associated phase is an instruction which updates a condition code, means for indicating whether or not a condition code has already been determined, a register for holding the determined condition code, and means for deciding, in response to outputs of those three means, whether or not one of instructions preceding a conditional branch instruction which updates a condition code last, has determined the code. This further promotes fast determination of success/failure of branching. Nevertheless, the proposed system is not applicable to a system having a plurality of operation pipelines or a system, if with a single operation pipeline, having a plurality of circuits capable of determining condition codes in the same phase in the pipeline processing procedure.